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Farnell introduces latest Raspberry Pi innovation
29 August 2024
RENOWNED DISTRIBUTOR of products and technology for electronic and industrial system design, maintenance and repair, Farnell is now offering customers the opportunity to order the tiny, fast, and versatile Raspberry Pi Pico 2.
This latest innovation from Raspberry Pi conveniently retains the footprint of the original Pico, while benefiting from the performance uplift delivered by the brand-new RP2350 microcontroller, designed by Raspberry Pi.
When compared to its predecessor, the acclaimed RP2040 microcontroller launched in 2021, RP2350 offers a 150MHz system clock (versus 133MHz); dual Arm Cortex-M33 cores (versus dual Arm Cortex-M0+); dual Hazard3 RISC-V cores; 520KB SRAM (versus 264KB); 8KB on-chip antifuse OTP storage; a comprehensive security model, based on Arm TrustZone for Cortex-M; and greatly improved power efficiency.
Raspberry Pi Pico 2 pairs RP2350 with 4MB of on-board flash memory (versus 2MB on Raspberry Pi Pico) for code and data storage.
Eben Upton, CEO at Raspberry Pi said: “We are excited to be bringing to market our second-generation microcontroller, RP2350, and the Raspberry Pi Pico 2 single-board computer. Offering higher performance, lower power consumption, and greater security, these products provide our enthusiast and design engineer customers with an unparalleled platform for experimentation and innovation. We look forward to seeing what projects and products they create.”
Simon Wade, senior global product manager, single board computing, at Farnell, said: “Raspberry Pi products remain as popular as ever with our customers and we are sure that this latest offering, the Raspberry Pi Pico 2, will be no different. The enhanced features deliver a real step-change compared with the original Pico and, with the launch of this innovative product, it is an exciting time for enthusiasts across the globe.”
Key security features of RP2350 include: OTP for boot configuration and key storage; support in ROM for stage 2 bootloader authentication using a public key fingerprint in OTP; and system infrastructure supporting for Arm TrustZone for Cortex-M.
The RP2350 peripheral set comprises: 2 UARTs; 2 SPI controllers; 2 I2C controllers; 24 PWM channels; a USB 1.1 controller and PHY with host and device support; and 12 PIO state machines. An enhanced QSPI interface provides a double-banked cache for higher hit bandwidth, and supports flash and PSRAM, burst transfers, odd clock divisors, and address translation.
As with the roll-out of its predecessor RP2040, a number of third-party products developed specifically in anticipation of the introduction of the RP2350 are also being introduced.
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